The present invention relates to a semiconductor integrated circuit (IC) device designed by using a computer and, more particularly, to a large-scale IC (LSI) made by the multi-layer aluminum wiring technique.
Computer-aided designing (CAD) of LSIs employs the so-called polycell technique disclosed in IEEE Journal of Solid-State Circuits, CH1726-9/82, pp. 111-114, 1982, and in Japanese Patent Application No. 51-74627 of the present applicants. High-speed operation and high integration of the semiconductor IC device made by the polycell technique are stated in U.S. patent application Ser. No. 709,107 filed Mar. 7, 1985. These references do not describe how to form a via contact hole to decrease errors and increase the packing density of the device when an aluminum layer extends through the hole and is connected to another aluminum layer.
The known polycell technique can be applied to produce two types of LSIs. The first type is made in the following manner. A first insulating layer is formed on a semiconductor substrate. A polysilicon wiring layer is formed on a selected portion of the first insulating layer. A second insulating layer is formed on the first insulating layer and also on the polysilicon wiring layer. A first aluminum wiring layer is formed on the second insulating layer, and a third insulating layer is formed on the first aluminum wiring layer. A via contact hole is then cut in the third insulating layer, vertically aligned with the polysilicon wiring layer. A second aluminum wiring layer is formed on the third insulating layer. Aluminum fills up the hole, whereby the second aluminum wiring layer is connected to the first aluminum layer.
An LSI of the second type is manufactured in the following method. A diffusion wiring layer is formed in a major surface of a semiconductor substrate. A first insulating layer is formed on this layer. A second insulating layer is formed on the first insulating layer. A first aluminum wiring layer is formed on the second insulating layer. A third insulating layer is formed on the first aluminum wiring layer. A via contact hole is then made in the third insulating layer, vertically aligned with the diffusion wiring layer. A second aluminum wiring layer is formed on the second insulating layer. Aluminum fills up the hole, whereby the second aluminum wiring layer is connected to the first aluminum layer.
In the LSI of the first type, the polysilicon wiring layer is formed on a portion of the first insulating layer, not on the entire surface thereof. All layers formed above polysilicon wiring layer are inevitably curved. In the LSI of the second type, the diffusion wiring layer is formed in the same step as sn element region (e.g., the source and drain regions of a MOS transistor), that portion of the first insulating layer which is formed on the diffusion wiring layer is thinner than the other portions. Hence, all layers formed above the first insulating layer are curved.
Here arises a problem with both LSIs when the via contact hole is made in the third insulating layer by applying a light beam to a photoresist layer formed on the third insulating layer. The beam is irregularly reflected when applied on the curving portion of the photoresist layer. This irregular reflection makes it impossible to cut a hole of an arcuate diameter at the desired position. In other words, misalignment of the via contact hole with the polysilicon wiring layer or the diffusion wiring layer occurs. Consequently, the second aluminum layer is short-circuited to the substrate. This causes an incomplete connection between the first and second aluminum wiring layers.